Advances in the miniaturization of complementary-metal-oxide-semiconductor (CMOS) devices have been a key driving force behind the explosive growth of various network centric computing products such as ASIC high-speed microprocessors and memories, low power hand-held computing devices and advanced multi-media audio and video devices. Smaller CMOS devices typically equate to faster switching times which in turn lead to faster and better performing end user systems.
It is well known that as the contact area decreases, contact resistance increases, and as the active semiconductor dopant level at the contact surface increases, contact resistance between a metal or other contact layer and the semiconductor decrease. Since resistance at the Schottky (metal/semiconductor) interface of the source/drain electrode is generally the largest component of total electrode resistance in MOS devices, it is expected to have the largest impact on device speed.
Traditional MOS transistors often use metal silicide layers. Before silicide processing, the source/drain (S/D) implants are performed then annealed at a high temperature (e.g. >950 C) to achieve a high percentage of active dopant relative to the chemical dopant provided, such as at least 30% for both the n+ and p+ regions. A self-aligned silicidation process (salicide) is often used to form the region of titanium, cobalt or tungsten silicide on the gate electrode and source/drain regions of the MOS transistor. In this process, the area to be silicided is generally rendered amorphous in a pre-amorphization (PA) step prior to silicidation to help prevent the formation of micro-defects commonly referred to as pipes which can result in shorts or increased leakage between spaced apart impurity regions of semiconductor devices that need to be electrically isolated from one another for proper device operation. However, the PA process is known to deactivate essentially all of the source and drain dopant in the surface through a depth of at least about 300 A.
One previous solution to the silicide interface resistance problem involves use of a higher reaction temperature capable silicide to provide a higher active dopant concentration. For example, Ni—Pt silicides, instead of Ni, allows increasing the reaction temperature to about 475-500 C. However, while a modest improvement generally results, the improvement is not sufficient to overcome the reduction in doping concentration at state of the art processes, such as at the 45 nm node.
Due to silicide integrity concerns for silicides, including Ni or NiPt silicides, the maximum temperature generally allowed after metal interface layer deposition (e.g. NiPt) is generally less than 500 C, such as about 475 C. Temperatures over about 500 C. are known to lead to yield issues mainly due to silicide agglomeration. Agglomeration is present whether the silicide is NiPt or not (NiPt generally being the silicide having the highest known temperature tolerance). While the agglomeration related failures generally do not result in hard failures (i.e. some devices will work), the fraction of failed devices increases substantially as the temperature is increased and the junction depth is decreased, reducing the yield to an unacceptable level for many processes.
As a result of the temperature limitation to less than about 475 C, the silicide anneal upon which recrystallization takes place only partially reactivates the dopant within about 300 A of the surface, such as to a level of about 10%. For a conventional process where the surface dopant surface concentration is about 1020 cm−3, the active surface concentration (which as noted above determines the interface resistance) becomes only about 1×1019 cm−3. Accordingly, there is a tradeoff in current processing between high circuit yield resulting from the minimization of pipes and other defects and low silicide interface resistance and accompanying improved transistor speed. Moreover, too high a doping concentration is known to result in an increase in SCE. What is needed is a process and resulting MOS device design that provides both high yield (minimization of pipes and other crystal defects), low silicide interface resistance allowing higher drive current, faster MOS transistor performance, and good short channel behavior.